III-V nanowire FET with compositionally-graded channel and wide-bandgap core

ABSTRACT

A method for fabricating a III-V nanowire. The method may include providing a semiconductor substrate, which includes an insulator, with a wide-bandgap layer on the top surface of the semiconductor substrate; etching the insulator to suspend the wide-bandgap layer; growing a compositionally-graded channel shell over the wide-bandgap layer; forming a gate structure forming spacers on the sidewalls of the gate structure; and forming a doped raised source drain region adjacent to the spacers.

BACKGROUND OF THE INVENTION

The present invention relates generally to semiconductor devices, andmore particularly to III-V nanowire FETs with a compositionally-gradedchannel shell around a wide-bandgap core and methods of theirfabrication.

The fabrication of semiconductor devices involves forming electroniccomponents in and on semiconductor substrates, such as silicon wafers.These electronic components may include one or more conductive layers,one or more insulation layers, and doped regions formed by addingvarious dopants into portions of a semiconductor substrate to achievespecific electrical properties. Semiconductor devices includetransistors, diodes, resistors, capacitors, and the like, withintermediate and overlying metallization patterns at varying levels,separated by dielectric materials, which interconnect the semiconductordevices to form integrated circuits.

Field-effect transistors (FETs) are a commonly used semiconductordevice. Generally, a FET has three terminals, i.e., a gate structure orgate stack to control the charge in a channel region, a source region,and a drain region. The gate stack is a structure used to control outputcurrent, i.e., flow of carriers in the channel portion of an FET,through electrical fields. The channel portion of the substrate is theregion between the source region and the drain region of a semiconductordevice that becomes conductive when certain voltage is applied to thegate. The source region is a doped region in the semiconductor devicefrom which majority carriers are flowing into the channel portion. Thedrain region is a doped region in the semiconductor device located atthe end of the channel portion, in which carriers are flowing into fromthe source region via the channel portion and out of the semiconductordevice through the drain region.

In nanowire FETs with uniform channel material, the charge centroid andthe maximum leaking point in the sub-threshold regime is the center ofthe nanowire. In materials with substantial conduction band offset, ifthe center region or core of the nanowire has a wider bandgap material,and/or the nanowire channel has compositional grading, then the chargeof the centroid and the maximum leakage point will move to the outerchannel region and become closer to the gate. This often leads toimproved gate control over the nanowire channel in the sub-thresholdregime and better control of short-channel effects. The use of widerbandgap material in the inner region of the nanowire also often reducesoff-state leakage due to tunneling (i.e., direct source-to-draintunneling and band-to-band tunneling). However, some nanowire FETsmaterial systems have a conduction band offset that is zero, or close tozero, making it difficult to improve gate control and short-channeleffects.

SUMMARY

According to one embodiment of the present invention, a method forfabricating a III-V nanowire is provided, the method comprising:providing a semiconductor substrate comprising an insulator, wherein awide-bandgap layer is disposed on a top surface of the semiconductorsubstrate; etching the insulator to suspend the wide-bandgap layer;growing a compositionally-graded channel shell over the wide-bandgaplayer; forming a gate structure and spacers, wherein the spacers areformed on sidewalls of the gate structure; and forming a doped raisedsource drain region adjacent to the spacers.

According to another embodiment of the present invention, asemiconductor structure is provided, the semiconductor structurecomprising: a wide-bandgap layer disposed on a semiconductor substrate;a nanowire FET disposed above said semiconductor substrate, wherein saidnanowire FET comprises a compositionally-graded channel shell; a gatestructure, such that a portion of the gate structure is disposed on saidnanowire FET, wherein spacers are formed on sidewalls of the gatestructure; and a doped III-V raised source drain region around saidcompositionally-graded channel shell, wherein a doped III-V raisedsource drain is configured to facilitate conductivity in the doped III-Vraised source drain region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B depict a plan view and a cross-sectional view of asemiconductor starting wafer, in accordance with an embodiment of thepresent invention;

FIGS. 2A and 2B depict a plan view and a cross-sectional view of thesemiconductor starting wafer of FIGS. 1A and 1B after the nanowireregion is defined by anchor pads, in accordance with an embodiment ofthe present invention;

FIGS. 3A and 3B depict a plan view and a cross-sectional view of thesemiconductor after the etching of a recess below the nanowire, inaccordance with an embodiment of the present invention;

FIGS. 4A and 4B depict a plan view and a cross-sectional view of thesemiconductor after the formation of a compositionally-graded channelshell, in accordance with an embodiment of the present invention;

FIGS. 5A-5C depict a plan view and cross-sectional views of thesemiconductor after the formation of a gate structure, in accordancewith an embodiment of the present invention;

FIGS. 6A and 6B depict a plan view and a cross-sectional view of thesemiconductor after the formation of spacers on the sidewalls of thegate structure of FIGS. 5A-5C, in accordance with an embodiment of thepresent invention;

FIGS. 7A and 7B depict a plan view and a cross-sectional view of thesemiconductor after the formation of a doped raised source drain region,in accordance with an embodiment of the present invention;

FIG. 8 depicts an example of a cross-sectional view of an FET aftersemiconductor processing is complete, in accordance with an embodimentof the present invention;

FIG. 9A depicts an example graph of the gate voltage as a function ofthe sheet carrier charge in the channel for various FET structures, inaccordance with an embodiment of the present invention; and

FIG. 9B depicts an example of an electron energy and concentration graphfor various FET structures, in accordance with an embodiment of thepresent invention.

DETAILED DESCRIPTION

Embodiments of the present invention describe III-V nanowire FETs withcompositionally-graded channel shells and wide-bandgap cores. Detaileddescription of embodiments of the claimed structures and methods aredisclosed herein; however, it is to be understood that the disclosedembodiments are merely illustrative of the claimed structures andmethods that may be embodied in various forms. In addition, each of theexamples given in connection with the various embodiments is intended tobe illustrative, and not restrictive. Further, the figures are notnecessarily to scale; some features may be exaggerated to show detailsof particular components. Therefore, specific structural and functionaldetails disclosed herein are not to be interpreted as limiting, butmerely as a representative basis for teaching one skilled in the art tovariously employ the methods and structures of the present disclosure.

References in the specification to “one embodiment”, “an embodiment”,“an example embodiment”, etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

For purposes of the description hereinafter, the terms “upper”, “lower”,“right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, andderivatives thereof shall relate to the disclosed structures andmethods, as oriented in the drawing Figures. The terms “on”, “over”,“overlying”, “atop”, “positioned on”, or “positioned atop” mean that afirst element, such as a first structure, is present on a secondelement, such as a second structure, wherein intervening elements, suchas an interface structure, may be present between the first element andthe second element. The terms “direct contact”, “directly on”, or“directly over” mean that a first element, such as a first structure,and a second element, such as a second structure, are connected withoutany intermediary conducting, insulating or semiconductor layers at theinterface of the two elements. The terms “connected” or “coupled” meanthat one element is directly connected or coupled to another element, orintervening elements may be present. The terms “directly connected” or“directly coupled” mean that one element is connected or coupled toanother element without any intermediary elements present.

Sequential steps of an exemplary embodiment of a method for fabricationof a III-V nanowire FET with a compositionally-graded channel shell anda wide-bandgap core are described below with respect to FIGS. 1-8.

Referring now to the figures, FIG. 1A depicts a plan view of asemiconductor starting wafer 100 upon which embodiments of the presentinvention may be fabricated, and FIG. 1B depicts a cross-sectional viewof FIG. 1A, taken along the line 1B-1B of FIG. 1A. In this exemplaryembodiment, starting wafer 100 includes substrate 101, buried oxide(BOX) 102 and wide-band-gap III-V semiconductor 103. A person of skillin the art will recognize that starting wafer 100 can be composed of anystandard starting material used in the art. In an example, if startingwafer 100 is used for making a semiconductor device, then starting wafer100 is a single-crystal semiconductor wafer. In this exemplaryembodiment, substrate 101 is composed of a silicon containing material,such as Si, single crystal Si, SiGe, single crystal silicon germanium,or combinations and multi-layers thereof. BOX 102 acts as an insultinglayer formed over substrate 101. Wide-bandgap III-V semiconductor 103 isa thin layer, for example, from 3 nm to 10 nm in thickness, and is usedas the seed for the epitaxy of the compositionally-graded nanowirechannel shell. Wide-bandgap III-V semiconductor 103 is composed ofcolumn III and V elements and may be, for example, indium phosphide(InP), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), orindium aluminum arsenide (InAlAs). In this exemplary embodiment,wide-bandgap III-V semiconductor 103 is composed of a starting materialof InP or InAlAs. In other embodiments of the present invention,silicon-on-insulator or germanium-on-insulator (i.e., SOI or GeOI)substrates may be used as a starting wafer.

Referring now to FIGS. 2A and 2B, FIG. 2A depicts a plan view of thesemiconductor starting wafer 100 of FIGS. 1A and 1B after the nanowireregion is defined by anchor pads 104, and FIG. 2B depicts across-sectional view of FIG. 2A, taken along the line 2B-2B of FIG. 2A.As depicted in FIGS. 2A and 2B, lithography techniques are used todefine the nanowire region with anchor pads 104. The position of anchorpads 104 is shown in a plan view of the semiconductor in FIG. 2A. Inthis exemplary embodiment, a photolithography process known in the artis used, and the nanowire region containing anchor pads 104 is coveredwith a photoresist (PR). Wide-bandgap III-V semiconductor 103 is thenetched out from regions not covered with the photoresist by any etchprocesses known in the art, such as reactive ion etching (RIE), asdepicted in FIGS. 2A and 2B. The etching process is typically chosen sothe etching chemistry is selective with respect to wide-bandgap III-Vsemiconductor 103.

Referring now to FIGS. 3A and 3B, FIG. 3A depicts a plan view of thesemiconductor after the etching of recess 105 below the nanowire, andFIG. 3B depicts a cross-sectional view of FIG. 3A, take along the line3B-3B of FIG. 3A. In this exemplary embodiment, the insulating layer,BOX 102, is etched out to form recess 105 below the nanowire, using anisotropic etching process known in the art. For example, dilutedhydrofluoric acid (DHF) can be used to undercut BOX 102 under thenanowire. In this exemplary embodiment, BOX 102 is only etched out inthe region below the nanowire which is not covered by anchor pads 104.Anchor pads 104 are much larger than the nanowire width, thus the oxiderecess yields a nanowire that is suspended between anchor pads 104.

Referring now to FIGS. 4A and 4B, FIG. 4A depicts a plan view of thesemiconductor after the formation of compositionally-graded channelshell 106, and FIG. 4B depicts a cross-sectional view of FIG. 4A, takenalong the line 4B-4B of FIG. 4A. Compositionally-graded channel shell106 is formed using selective epitaxial growth processes, such asmetal-organic chemical vapor deposition (MOCVD) or atomic layerdeposition (ALD), and may have a thickness of approximately 5 nm to 20nm. After the growth of compositionally-graded channel shell 106,wide-bandgap III-V semiconductor 103 acts like a core and, therefore, isalso referred to as a wide-bandgap core (hereinafter referred to as“wide-bandgap core 103”). The grading of the channel shell creates abuilt-in field on the semiconductor. In this exemplary embodiment,wide-bandgap core 103 is composed of GaAs, and compositionally-gradedchannel shell 106 material starts as In_(0.2)Ga_(0.8)As closest towide-bandgap core 103, where the In content in the ternary alloy is 20%and the Ga content is 80%. As the distance from wide-bandgap core 103increases, the percentage of In content then increases to 53%, while theGa content decreases to 47% and, at an even farther distance fromwide-bandgap core 103, the In content increases further to 72%, whilethe Ga content drops further to 28%. In yet another embodiment,wide-bandgap core 103 is composed of aluminum arsenide (AlAs) andcompositionally-graded channel shell 106 material starts asAl_(x)Ga_(1-x)As with x=1, which is then graded all the way to GaAs,where x=0, at the outer surface of compositionally-graded channel shell106. The grading profile (i.e., the change of composition ‘x’ in theradial direction) can be linear, or take other mathematical forms.

Referring now to FIGS. 5A-5C, FIG. 5A depicts a plan view of thesemiconductor after the formation of gate-all-around structure 107, FIG.5B depicts a cross-sectional view of FIG. 5B, taken along the line 5B-5Bof FIG. 5A, and FIG. 5C depicts a cross-sectional view of FIG. 5A, takenalong the line 5C-5C. As depicted in FIG. 5C, gate-all-around structure107 includes gate dielectric 107 c, gate electrode 107 b, and gate hardmask 107 a. In a gate-all-around structure, gate dielectric 107 c andgate electrode 107 b surround the nanowire channel. A conformal gatedielectric 107 c is deposited using a suitable deposition techniqueincluding, but not limited to, ALD, chemical vapor deposition (CVD),plasma-enhanced chemical vapor deposition (PECVD), or any otherconformal deposition process. Gate dielectric 107 c may be composed ofany appropriate gate dielectric material, including, but not limited to,SiO₂, HfO₂, ZrO₂, Al₂O₃, La₂O₃, Y₂O₃, LaAlO₃, HfSiO₂, and SrTiO₃. Gateelectrode 107 b is then deposited on gate dielectric 107 a. In thisexemplary embodiment, the deposition is conformal to fabricate agate-all-around structure. Gate electrode 107 b is deposited by a knowndeposition method such as CVD, PECVD, ALD, physical vapor deposition(PVD), or other similar known deposition methods. Gate electrode 107 bmay be composed of any suitable conductive material for a gateelectrode, including, but not limited to, Ti, TiN, Ta, TaN, doped polySi, doped poly SiGe, and doped poly Ge. Finally, gate hard mask 107 a isdeposited on gate electrode 107 b. Gate hard mask 107 a is deposited bya known deposition method such as CVD, PECVD, ALD, or other similarknown deposition methods. Gate hard mask 107 a may be composed of anysuitable insulating material including, but not limited to, SiN andSiO₂. Gate-all-around structure 107 is then patterned using standardlithography and etching techniques known in the art, such as thosedescribed above. As depicted in FIG. 5B, compositionally-graded channelshell 106 encompasses wide-bandgap core 103, and gate-all-aroundstructure 107 (i.e., gate dielectric 107 c, gate electrode 107 b, andgate hard mask 107 a) fully encompasses the core/graded channelstructure.

Referring now to FIGS. 6A and 6B, FIG. 6A depicts a plan view of thesemiconductor after the formation of spacers 108 on the sidewalls ofgate-all-around structure 107 of FIGS. 5A-5C, and FIG. 6B depicts across-sectional view of FIG. 6A, taken along the line 6B-6B of FIG. 6A.Spacers 108 may be composed of any dielectric, such as a nitride (e.g.,SiN), an oxide (e.g., SiO₂), an oxynitride, or a combination thereof.The dielectric material of spacers 108 may be deposited through, forexample, chemical vapor deposition (CVD). The dielectric material isthen etched using an anisotropic etching process, such as reactive ionetching (RIE), to form spacers 108.

Referring now to FIGS. 7A and 7B, FIG. 7A depicts a plan view of thesemiconductor after the formation of doped III-V raised source drain(RSD) region 109, and FIG. 7B depicts a cross-sectional view of FIG. 7A,taken along the line 7B-7B of FIG. 7A. RSD region 109 is formed usingselective epitaxial growth processes, such as MOCVD or ALD. In thisexemplary embodiment RSD region 109 is doped in-situ (i.e., during theepitaxial growth) with dopant appropriate for the FET type. For example,III-V NFETs are doped with Si, Se, or Te, while III-V PFETs are dopedwith Zn or C. RSD region 109 facilitates conductivity in thesource/drain regions and increases the volume of material that may offerlower series resistance. In some embodiments, RSD region(s) 109 fromadjacent nanowires are capable of merging and forming a new anchor pad,where contact vias may be dropped when there is a tight nanowire pitch.

FIG. 8 depicts a cross-sectional view of the FET after the completion ofsemiconductor processing, in accordance with an embodiment of thepresent invention. FET processing is completed through the formation ofa metal-III-V alloy 110, planarization using interlayer dielectric (ILD)111, and the formation of contact vias 112, which are standard processesknown in the art.

FIG. 9A depicts an example graph in which the gate voltage (VG) isplotted as a function of the sheet carrier charge in the channel(N_(s)), for a plurality of FETs (FET 901-904). FET 901 is a 10 nmInGaAs 50% nanowire, with uniform grading throughout. FET 902 is a 10 nmInGaAs nanowire, where 100% is InAs, with uniform grading throughout.FET 903 is a 10 nm InGaAs nanowire with a linear grading from 100% to50%. FET 904 is a 10 nm InGaAs nanowire with a linear grading from 100%to 50%, and a 3 nm core. As depicted in FIG. 9A, FET 904 has a lowerN_(s) in the inversion regime, due to a larger wave function spread anda smaller density-of-states capacitance CDOS. The graded channel FETs,FET 901 and FET 902 have a higher N_(s) than the In_(0.53)Ga_(0.47)Aschannel FET in the inversion regime, because the wave function spread ina graded channel FET is much smaller due to the built-in field createdby the grading.

FIG. 9B depicts an example graph in which the depth (A) is plotted as afunction of electron concentration (cm-3) for a plurality of FETs (FET901-904), the composition of which is the same as described above inFIG. 9A. As depicted in FIG. 9B, the gradual change in electronconcentration going from one region of the compositionally-gradedchannel to another region is apparent in the graded FETs (FET 901 andFET 902), while there is relatively little change in electronconcentration in the uniform FETs (FET 903 and FET 904). FET 901 and FET902 show a decrease in electron concentration going toward thewide-bandgap core (i.e., from approximately 50 A to 100 A), with thelowest electron concentration at the center of the wide-bandgap core(i.e., approximately 100 A). Moving away from the core and toward theouter shell of the graded-channel (i.e., from approximately 100 A to 150A), the electron concentration increases, which correlates with thegrading composition as described above with respect of FIG. 4.

Having described embodiments for a III-V nanowire FET with acompositionally-graded channel shell around a wide-bandgap core withreduced short channel effects and methods of fabrication (which areintended to be illustrative and not limiting), it is noted thatmodifications and variations may be made by persons skilled in the artin light of the above teachings. It is, therefore, to be understood thatchanges may be made in the particular embodiments disclosed which arewithin the scope of the invention as outlined by the appended claims.

In certain embodiments, the fabrication steps depicted above may beincluded on a semiconductor substrate consisting of many devices and oneor more wiring levels to form an integrated circuit chip.

The resulting integrated circuit chips can be distributed by thefabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case, the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications, to advanced computer products having a display, a keyboardor other input device, and a central processor.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

What is claimed is:
 1. A semiconductor structure comprising: awide-bandgap layer disposed on a semiconductor substrate; a nanowire FETdisposed above said semiconductor substrate, wherein said nanowire FETcomprises a compositionally-graded channel shell; a gate structure,wherein at least a portion of the gate structure is disposed on saidnanowire FET; spacers formed on sidewalls of the gate structure; and adoped III-V raised source drain region around saidcompositionally-graded channel shell, wherein a doped III-V raisedsource drain is configured to facilitate conductivity in the doped III-Vraised source drain region.
 2. The semiconductor structure of claim 1,wherein the gate structure comprises a gate-all-around structure with acompositionally-graded channel shell.
 3. The semiconductor structure ofclaim 1, wherein the wide-bandgap layer is comprised of column III and Velements.
 4. The semiconductor structure of claim 1, wherein thecompositionally-graded channel shell comprises a column III element anda column V element.
 5. The semiconductor structure of claim 4, whereinthe compositionally-graded channel shell comprising column III andcolumn V elements comprises a material composition of In_(0.2)Ga_(0.8)Asthat compositionally grades to a material composition ofIn_(0.72)Ga_(0.28)As, wherein the material composition ofIn_(0.2)Ga_(0.8)As is disposed farther from a gate electrode than thematerial composition of In_(0.72)Ga_(0.28)As.
 6. The semiconductorstructure of claim 1, wherein the gate structure comprises a gatedielectric, a gate electrode, and a gate hard mask.
 7. The semiconductorstructure of claim 1, wherein the wide-bandgap layer has a thicknessthat is greater than or equal to 3 nm and less than or equal to 10 nm.8. The semiconductor structure of claim 1, wherein thecompositionally-graded channel shell has a thickness that is greaterthan or equal to 5 nm and less than or equal to 20 nm.
 9. Thesemiconductor structure of claim 1, wherein the semiconductor substratecomprises silicon-on-insulator (SOI) or germanium-on-insulator (GeoI) onburied oxide (BOX).
 10. The semiconductor structure of claim 1, whereinsaid wide-bandgap layer comprises a starting material composition ofInP.
 11. The semiconductor structure of claim 1, wherein saidwide-bandgap layer comprises a starting material composition of InAlAs.